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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. a ad9834 20 mw power, 2.3 v to 5.5 v, 50 mhz complete dds features narrow-band sfdr >72 db 2.3 v to 5.5 v power supply 50 mhz ref clock, 0 mhz to 25 mhz output sine output/triangular output on-board comparator 3-wire spi interface extended temperature range: ?0 c to +105 c power-down option 20 mw power consumption at 3 v 20-lead tssop package applications frequency stimulus/waveform generation frequency phase tuning and modulation low power rf/communications systems liquid and gas flow measurement sensory applications?roximity, motion, and defect detection test and medical equipment functional block diagram 12 s 10-bit dac phase accumulator (28-bit) mux 28-bit freq0 reg mux on-board reference full-scale control comparator divided by 2 msb cap/2.5v dvdd agnd avdd mclk ad9834 fsync sclk sdata serial interface and control logic comp vcc 2.5v iout ioutb dgnd regulator refout fs adjust vin fselect 28-bit freq1 reg 12-bit phase0 reg 12-bit phase1 reg 16-bit control register sleep reset pselect mux sin rom mux mux sign bit out general description the ad9834 is a 50 mhz low power dds device capable of producing high performance sine and triangular outputs. it also has an on-board comparator that allows a square wave to be produced for clock generation. consuming only 20 mw of power at 3 v makes the ad9834 an ideal candidate for power- sensitive applications. capability for phase modulation and frequency modulation is provided. the frequency registers are 28 bits; with a 50 mhz clock rate, resolution of 0.2 hz can be achieved. similarly, with a 1 mhz clock rate, the ad9834 can be tuned to 0.004 hz resolution. frequency and phase modulation are affected by loading registers through the serial interface and toggling the registers using software or the fselect/pselect pins, respectively. the ad9834 is written to via a 3-wire serial interface. this serial interface operates at clock rates up to 40 mhz and is compatible with dsp and microcontroller standards. the device operates with a power supply from 2.3 v to 5.5 v. the analog and digital sections are independent and can be run from different power supplies, e.g., avdd can equal 5 v with dvdd equal to 3 v. the ad9834 has a power-down pin (sleep) that allows exter- nal control of the power-down mode. sections of the device that are not being used can be powered down to minimize the current consumption, e.g., the dac can be powered down when a clock output is being generated. t he part is available in a 20-lead tssop package.
rev. 0 e2e ad9834especifications 1 parameter min typ max unit test conditions/comments signal dac specifications resolution 10 bits update rate 50 msps i out full scale 2 3.0 ma v out max 0.6 v v out min 30 mv output compliance 3 0.8 v dc accuracy integral nonlinearity 1 lsb differential nonlinearity 0.5 lsb dds specifications dynamic specifications signal-to-noise ratio 55 60 db f mclk = 50 mhz, f out = f mclk /4096 total harmonic distortion e66 e56 dbc f mclk = 50 mhz, f out = f mclk /4096 spurious-free dynamic range (sfdr) wideband (0 to nyquist) e60 e56 dbc f mclk = 50 mhz, f out = f mclk /50 narrow band ( 200 khz) e78 e67 dbc f mclk = 50 mhz, f out = f mclk /50 clock feedthrough e50 dbc wake-up time 1 ms comparator input voltage range 1 v p-p ac-coupled internally input capacitance 10 pf input high-pass cutoff frequency 4 mhz input dc resistance 5 m w input leakage current 10 m a output buffer output rise/fall time 12 ns using a 15 pf load output jitter 120 ps rms 3 mhz sine wave 0.6 v p-p voltage reference internal reference 1.12 1.18 1.24 v refout output impedance 4 1k w reference tc 100 ppm/
rev. 0 ad9834 ? iout 12 10-bit dac sin rom 20pf fs adjust ad9834 r set 6.8k regulator 100nf cap/2.5v on-board reference full-scale control 10nf refout 200 comp 10nf avdd r load figure 1. test circuit used to test the specifications timing characteristics 1 parameter limit at t min to t max unit test conditions/comments t 1 20 ns min mclk period t 2 8 ns min mclk high duration t 3 8 ns min mclk low duration t 4 25 ns min sclk period t 5 10 ns min sclk high duration t 6 10 ns min sclk low duration t 7 5 ns min fsync to sclk falling edge setup time t 8 min 10 ns min fsync to sclk hold time t 8 max t 4 ? ns max t 9 5 ns min data setup time t 10 3 ns min data hold time t 11 8 ns min fselect, pselect setup time before mclk rising edge t 11a 8 ns min fselect, pselect setup time after mclk rising edge t 12 5 ns min sclk high to fsync falling edge setup time 1 guaranteed by design, not production tested. mclk t 2 t 1 t 3 figure 2. master clock valid data valid data valid data mclk fselect, pselect t 11a t 11 figure 3. control timing sclk fsync sdata t 5 t 4 t 6 t 7 t 8 t 10 t 9 d15 d14 d2 d1 d0 d15 d14 t 12 figure 4. serial timing (dvdd = 2.3 v to 5.5 v, agnd = dgnd = 0 v, unless otherwise noted.)
rev. 0 e4e ad9834 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9834 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings * (t a = 25 ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 143 jc thermal impedance . . . . . . . . . . . . . . . . . . . . . . 45
rev. 0 ad9834 e5e pin functions descriptions pin number mnemonic function analog signal and reference 1f s adjust full-scale adjust control. a resistor (r set ) is connected between this pin and agnd. this determines the magnitude of the full-scale dac current. the relationship between r set and the full-scale current is as follows: iout v /r full scale refout set = 18 vv nominal, r typical refout set == 120 68 ..k w 2 refout voltage reference output. the ad9834 has an internal 1.20 v reference that is made available at this pin. 3 comp dac bias pin. this pin is used for decoupling the dac bias voltage. 17 vin input to comparator. the comparator can be used to generate a square wave from the sinusoidal dac output. the dac output should be filtered appropriately before being applied to the co mparator to improve jitter. when bits opbiten and signpib in the control register are set to 1, the comparator input is connected to vin. 19, 20 iout, ioutb current output. this is a high impedance current source. a load resistor of nominally 200 w should be connected between iout and agnd. ioutb should preferably be tied through an external load resistor of 200 w to agnd, but can be tied directly to agnd. a 20 pf capacitor to agnd is also recommended to prevent clock feedthrough. power supply 4 avdd positive power supply for the analog section. avdd can have a value from 2.3 v to 5.5 v. a 0.1 m f decoupling capacitor should be connected between avdd and agnd. 5 dvdd positive power supply for the digital section. dvdd can have a value from 2.3 v to 5.5 v. a 0.1 m f decoupling capacitor should be connected between dvdd and dgnd. 6 cap/2.5v the digital circuitry operates from a 2.5 v power supply. this 2.5 v is generated from dvdd using an on-board regulator (when dvdd exceeds 2.7 v). the regulator requires a decoupling capacitor of typically 100 nf that is connected from cap/2.5v to dgnd. if dvdd is equal to or less than 2.7 v, cap/2.5v should be shorted to dvdd. 7 dgnd digital ground. 18 agnd analog ground. digital interface and control 8 mclk digital clock input. dds output frequencies are expressed as a binary fraction of the frequency of mclk. the output frequency accuracy and phase noise are determined by this clock. 9 fselect frequency select input. fselect controls which frequency register, freq0 or freq1, is used in the phase accumulator. the frequency register to be used can be selected using the pin fselect or the bit fsel. when the bit fsel is being used to select the frequency register, this pin, fselect, should be tied to cmos high or low. 10 pselect phase select input. pselect controls which phase register, phase0 or phase1, is added to the phase accumulator output. the phase register to be used can be selected using the pin pselect or the bit psel. when the phase registers are being controlled by the bit psel, this pin, pselect, should be tied to cmos high or low. 11 reset active high digital input. reset resets appropriate internal registers to zero, which corresponds to an analog output of midscale. reset does not affect any of the addressable registers. 12 sleep active high digital input. when this pin is high, the dac is powered down. this pin has the same function as control bit sleep12. 13 sdata serial data input. the 16-bit serial data-word is applied to this input. 14 sclk serial clock input. data is clocked into the ad9834 on each falling sclk edge. 15 fsync active low control input. this is the frame synchronization signal for the input data. when fsync is taken low, the internal logic is informed that a new word is being loaded into the de vice. 16 sign bit out logic output. the comparator output is available on this pin or, alternatively, the msb from the nco can be output on this pin. setting bit opbiten in the control register to 1 enables this output pin. bit signpib determines whether the comparator output or the msb from the nco is output on the pin.
rev. 0 e6e ad9834etypical performance characteristics mclk frequency e mhz i dd e ma 2.5 2.0 0 5 15 25 35 45 1.5 1.0 0.5 5v 3v t a = 25 c tpc 1. typical current consumption vs. mclk frequency e65 e60 e90 e70 e75 e80 e85 0510 15 20 25 30 35 40 45 50 mclk frequency mhz sfdr e dbc avdd = dvdd = 3v t a = 25 c sfdr db mclk/7 sfdr db mclk/50 tpc 4. wideband sfdr vs. mclk frequency 500 1000 700 650 600 550 850 750 800 900 950 e40 25 105 temperature e c wa ke-up time e s 5.5v 2.3v tpc 7. wake-up time vs. temperature f out e hz i dd e ma 4.0 0 100 0.5 1.0 1.5 2.0 2.5 3.0 3.5 1k 10k 100k 1m 10m 100m 3v 5v t a = 25 c tpc 2. typical i dd vs. f out for f mclk = 50 mhz f out / f mclk 0.001 0.01 100 0.1 1.0 10 sfdr e dbc 0 e40 e80 e50 e60 e70 e10 e20 e30 30 mhz clock 50 mhz clock av d d = dvdd = 3v t a = 25 c tpc 5. wideband sfdr vs. f out /f mclk for various mclk frequencies temperature e c v ( refout ) e v 1.150 1.125 e40 105 1.100 25 1.175 1.200 1.250 1.225 lower range upper range tpc 8. v refout vs. temperature 050 10 20 30 40 mclk frequency e mhz sfdr e dbc e65 e60 e90 e70 e75 e80 e85 sfdr db mclk/7 sfdr db mclk/50 a vdd = dvdd = 3v t a = 25 c tpc 3. narrow-band sfdr vs. mclk frequency mclk frequency e mhz 1.0 5.0 10 12.5 25 snr e db e60 e65 e70 e50 e55 e40 e45 50 avdd = dv dd = 3v f out = mclk/4096 t a = 25 c tpc 6. snr vs. mclk frequency frequency e hz dbc/hz e150 e110 e100 e120 e130 e140 e160 100 100k 1k 10k 200k a vdd = dvdd = 5v t a = 25 c tpc 9. output phase noise, f out = 2 mhz, mclk = 50 mhz
rev. 0 ad9834 e7e frequency e hz db 0 e20 e50 e90 e100 e80 e70 e60 e40 e30 e10 0 100k rwb 100 st 100 sec vwb 30 tpc 10. f mclk = 10 mhz; f out = 2.4 khz, frequency word = 000fba9 frequency e hz 0 e20 e50 e90 e100 e80 e70 e60 e40 e30 e10 0 160k rwb 100 st 200 sec vwb 30 db tpc 13. f mclk = 50 mhz; f out = 12 khz, frequency word = 000fba9 frequency e hz db 0 e20 e50 e90 e100 e80 e70 e60 e40 e30 e10 0 25m rwb 1k st 200 sec vwb 300 tpc 16. f mclk = 50 mhz; f out = 4.8 mhz, frequency word = 189374c frequency e hz db 0 e20 e50 e90 e100 e80 e70 e60 e40 e30 e10 0 5m rwb 1k st 50 sec vwb 300 tpc 11. f mclk = 10 mhz; f out = 1.43 mhz = f mclk /7, frequency word = 2492492 frequency e hz 0 e20 e50 e90 e100 e80 e70 e60 e40 e30 e10 0 1.6m rwb 100 st 200 sec vwb 300 db tpc 14. f mclk = 50 mhz; f out = 120 khz, frequency word = 009d496 frequency e hz db 0 e20 e50 e90 e100 e80 e70 e60 e40 e30 e10 0 25m rwb 1k st 200 sec vwb 300 tpc 17. f mclk = 50 mhz; f out = 7.143 mhz = f mclk /7, frequency word = 2492492 frequency e hz 0 e20 e50 e90 e100 e80 e70 e60 e40 e30 e10 0 5m rwb 1k st 50 sec vwb 300 db tpc 12. f mclk = 10 mhz; f out = 3.33 mhz = f mclk /3, frequency word = 5555555 frequency e hz 0 e20 e50 e90 e100 e80 e70 e60 e40 e30 e10 0 25m rwb 1k st 200 sec vwb 300 db tpc 15. f mclk = 50 mhz; f out = 1.2 mhz, frequency word = 0624dd3 frequency e hz db 0 e20 e50 e90 e100 e80 e70 e60 e40 e30 e10 0 25m rwb 1k st 200 sec vwb 300 tpc 18. f mclk = 50 mhz; f out = 16.667 mhz = f mclk /3, frequency word = 5555555
rev. 0 e8e ad9834 terminology integral nonlinearity this is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. the endpoints of the transfer function are zero scale, a point 0.5 lsb below the first code transition (000 . . . 00 to 000 ... 01) and full scale, a point 0.5 lsb above the last code transition (111 . . . 10 to 111 . . . 11). the error is expressed in lsbs. differential nonlinearity this is the difference between the measured and ideal 1 lsb change between two adjacent codes in the dac. a specified differ- ential nonlinearity of 1 lsb maximum ensures monoto nicity. output compliance the output compliance refers to the maximum voltage that can be generated at the output of the dac to meet the specifica- tions. when voltages greater than that specified for the output compliance are generated, the ad9834 may not meet the speci- fications listed in the data sheet. spurious-free dynamic range along with the frequency of interest, harmonics of the funda- mental frequency and images of these frequencies are present at the output of a dds device. the spurious-free dynamic range (sfdr) refers to the largest spur or harmonic present in the band of interest. the wideband sfdr gives the magnitude of the largest harmonic or spur relative to the magnitude of the fundamental frequency in the 0 to nyquist bandwidth. the narrow band sfdr gives the attenuation of the largest spur or harmonic in a bandwidth of 200 khz about the fundamental frequency. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the rms value of the fundamental. for the ad9834, thd is defined as: thd vvvvv v = ++++ 20 2 2 3 2 4 2 5 2 6 2 1 log where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. signal-to-noise ratio (snr) snr is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the n yquist frequency. the value for snr is expressed in decibels. clock feedthrough there will be feedthrough from the mclk input to the analog output. clock feedthrough refers to the magnitude of the mclk signal relative to the fundamental frequency in the ad9834?s output spectrum. theory of operation sine waves are typically thought of in terms of their magnitude form a(t) = sin ( t). however, these are nonlinear and not easy to generate except through piecewise construction. on the other hand, the angular information is linear in nature. that is, the phase angle rotates through a fixed angle for each unit of time. the angular rate depends on the frequency of the signal by the traditional rate of = 2 f . magnitude phase +1 0 e1 2p 0 2 4 6 2 4 6 figure 5. sine wave knowing that the phase of a sine wave is linear and given a reference interval (clock period), the phase rotation for that period can be determined. dd phase t =w solving for wp = = dd phase t f /2 solving for f and substituting the reference clock frequency for the reference period (1/ f mclk = t ) f phase f mclk = d /2 p the ad9834 builds the output based on this simple equation. a simple dds chip can implement this equation with three major subcircuits: numerically controlled oscillator + phase modulator, sin rom, and digital-to-analog convertor. each of these subcircuits is discussed in the following section. circuit description the ad9834 is a fully integrated direct digital synthesis ( dds) chip. the chip requires one reference clock, one low precision resistor, and eight decoupling capacitors to provide digitally created sine waves up to 25 mhz. in addition to the generation of this rf signal, the chip is fully capable of a broad range of simple and complex modulation schemes. these modulation schemes are fully implemented in the digital domain, allow- ing accurate and simple realization of complex modulation algo rithms using dsp techniques. the internal circuitry of the ad9834 consists of the following main sections: a numerically controlled oscillator (nco), frequency and phase modulators, sin rom, a digital-to- analog converter, a comparator, and a regulator. numerically controlled oscillator plus phase modulator this consists of two frequency select registers, a phase accumu- lator, two phase offset registers, and a phase offset adder. the main component of the nco is a 28-bit phase accumulator. con- tinuous time signals have a phase range of 0 to 2 . outside this range of num bers, the sinusoid functions repeat themselves in a periodic manner. the digital implementation is no different. the accumulator simply scales the range of phase numbers into a multibit digital word. the phase accumulator in the ad9834 is implem ented with 28 bits. therefore, in the ad9834, 2 = 2 28 . likewise, the phase term is scaled into this range of num- bers: 0 < phase < 2 28 e 1. making these substitutions into the equation above f phase f mclk = d /2 28 where 0 < phase < 2 28 e 1.
rev. 0 ad9834 e9e the input to the phase accumulator can be selected either from the freq0 register or freq1 register, and is controlled by the fselect pin or the fsel bit. ncos inherently generate continuous phase signals, thus avoiding any output discontinu- ity when switching between frequencies. following the nco, a phase offset can be added to perform phase modulation using the 12-bit phase registers. the contents of one of these phase registers is added to the most significant bits of the nco. the ad9834 has two phase registers, the resolu- tion of these registers being 2 /4096. sin rom to make the output from the nco useful, it must be converted f rom phase information into a sinusoidal value. since phase infor- mation maps directly into amplitude, the sin rom uses the digital phase information as an address to a look-up table and converts the phase information into amplitude. although the nco contains a 28-bit phase accumulator, the output of the nco is truncated to 12 bits. using the full resolution of the phase accumulator is impractical and unnecessary as this would require a look-up table of 2 28 entries. it is necessary only to have sufficient phase resolution such that the errors due to truncation are smaller than the resolution of the 10-bit dac. this requires the sin rom to have two bits of phase resolution more than the 10-bit dac. the sin rom is enabled using bits mode and opbiten in the control register. this is explained further in table xiv. digital-to-analog converter the ad9834 includes a high impedance current source 10-bit dac capable of driving a wide range of loads. the full-scale output current can be adjusted for optimum power and external load requirements through the use of a single external resistor (r set ). the dac can be configured for either single-ended or differen- tial operation. iout and ioutb can be connected through equal external resistors to agnd to develop complementary output voltages. the load resistors can be any value required, as long as the full-scale voltage developed across it does not exceed the voltage compliance range. si nce full-scale curren t is co n trolled by r set , adjustments to r set can balance changes made to the load resistors. comparator the ad9834 can be used to generate synth esized d igital clock signals. this can be done by using the on-board self-biasing comparator, which converts the dac?s sinusoidal signal to a square wave. the output from the dac may be filtered externally before being applied to the comparator input. the comparator reference voltage is the time average of the signal applied to v in . the comparator can accept signals in the range of approximately 100 mv p-p to 1 v p-p. as the comparator?s input is ac-coupled, to operate correctly as a zero crossing detector, it requires a minimum input frequency of typically 3 mhz. the comparator?s output will be a square wave with an amplitude from 0 v to dvdd. to enable the comparator, bits signpib and opbiten in the control resister are set to 1. this is explained further in table xiii. regulator the ad9834 has separate power supplies for the analog and digital sections. avdd provides the power supply required for the analog section, while dvdd provides the power supply for the digital section. both of these supplies can have a value of 2.3 v to 5.5 v and are independent of each other, e.g., the analog section can be operated at 5 v, and the digital section can be operated at 3 v, or vice versa. the internal digital section of the ad9834 is operated at 2.5 v. an on-board regulator steps down the voltage applied at dvdd to 2.5 v. the digital interface (serial port) of the ad9834 is also operated from dvdd. these digital signals are level shifted w ithin the ad9834 to make them 2.5 v compatible. when the applied voltage at the dvdd pin of the ad9834 is equal to or less than 2.7 v, the pins cap/2.5v and dvdd should be tied together, thus bypassing the on-board regulator. functional description serial interface the ad9834 has a standard 3-wire serial interface that is compatible with spi, qspi a , microwire a , and dsp inter- face standards. data is loaded into the device as a 16-bit word under the con trol of a serial clock input, sclk. the timing diagram for this op eration is given in figure 4. the fsync input is a level triggered input that acts as a frame synchronization and chip enable. data can only be transferred into the device when fsync is low. to start the serial data transfer, fsync should be taken low, observing the minimum fsync to sclk falling edge setup time, t 7 . after fsync goes low, serial data will be shifted into the device?s input shift register on the falling edges of sclk for 16 clock pulses. fsync may be taken high after the 16th falling edge of sclk, observ ing the minimum sclk falling edge to fsync rising edge time, t 8 . alternatively, fsync can be kept low for a multiple of 16 sclk pulses and then brought high at the end of the data transfer. in t his way, a continuous stream of 16-bit words can be loaded w hile fsync is held low, with fsync only going high after the 16th sclk falling edge of the last word is loaded. the sclk can be continuous, or alternatively, the sclk can idle high or low between write operations but must be high when fsync goes low (t 12 ). powering up the ad9834 the flow chart in figure 8 shows the operating routine for the ad9834. when the ad9834 is powered up, the part should be reset. this will reset appropriate internal registers to 0 to provide an analog output of midscale. to avoid spurious dac outputs while the ad9834 is being initialized, the reset bit/pin should be set to 1 until the part is ready to begin generating an output. reset does not reset the phase, frequency, or control registers. these registers will contain invalid data, and therefore should be set to a known value by the user. the reset bit/pin should then be set to 0 to begin generating an output. the data will appear on the dac output eight mclk cycles after reset is set to 0. latency associated with each operation is a latency. when the pins fselect and pselect change value, there is a pipeline delay before control is transferred to the selected register. when the timing specifications t 11 and t 11a are met (see figure 3), fselect and pselect have latencies of eight mclk cycles. when the timing specifications t 11 and t 11a are not met, the latency is increased by one mclk cycle.
rev. 0 e10e ad9834 similarly, there is a latency associated with each asynchronous write operation. if a selected frequency/phase register is loaded with a new word, there is a delay of eight to nine mclk cycles before the analog output will change. (there is an uncertainty of one mclk cycle as it depends on the position of the mclk rising edge when the data is loaded into the destination regis ter.) the negative transition of the reset and sleep functions are sampled on the internal falling edge of mclk, therefore they also have a latency associated with them. the control register the ad9834 contains a 16-bit control register that sets up the ad9834 as the user wishes to operate it. all control bits, except mode, are sampled on the internal negative edge of mclk. table ii describes the individual bits of the control register. the different functions and the various output options from the ad9834 are described in more detail in the section fol lowing table ii. to inform the ad9834 that the contents of the control register will be alterred, d15 and d14 must be set to 0 as shown b elow. table i. control register d15 d14 d13 d0 00 control bits sin rom phase accumulator (28-bit) (low power) 10-bit dac mux sleep12 sleep1 mode + opbiten opbiten iit otpt enbe iotb iot opto in inpib bb b b b b b e b pe b pin b eet b eep b eep b opbiten b inpib b i b b oe b iie b b inbitot b tii b b n b t b t bbt tit tii bb btb btbb tb bb b t bb tb bt bbb bbb bb bb e teee ti
rev. 0 ad9834 e11e table ii. description of bits in the control register (continued) bit name function d10 psel the psel bit defines whether the phase0 register or the phase1 register data is added to the output of the phase accumulator. see table v on selecting a phase register. d9 pin/sw functions that select frequency and phase registers, reset internal registers, and power down the dac can be i mpl e mented using either software or hardware. pin/sw selects the source of control for these functions. pin/sw = 1 implies that the functions are being controlled using the appropriate control pins. pin/sw = 0 implies that the functions are being controlled using the appropriate control bits. d8 reset reset = 1 resets internal registers to 0, which corresponds to an analog output of midscale. reset = 0 disables reset. this function is explained further in table xi. d7 sleep1 when sleep1 = 1, the internal mclk clock is disabled. the dac output will remain at its present value as the nco is no longer accumulating. w hen sleep1 = 0, mclk is enabled. this function is explained fur ther in table xii. d6 sleep12 sleep12 = 1 powers down the on-chip dac. this is useful when the ad9834 is used to output the msb of the dac data. sleep12 = 0 implies that the dac is active. this function is explained further in table xii. d5 opbiten the function of this bit is to control whether there is an output at the pin sign bit out. this bit should remain at 0 if the user is not using the pin sign bit out. opbiten = 1 enables the pin sign bit out. when opbiten equals 0, the sign bit out output buffer is put into a high impedance state, and therefore no output is available at the sign bit out pin. d4 signpib the function of this bit is to control what is output at the pin sign bit out. when signpib = 1, the on-board comparator is connected to sign bit out. after filtering the sinusoidal output from the dac, the waveform can be applied to the comparator to generate a square waveform. this is explained further in table xiii. when signpib = 0, the msb (or msb/2) of the dac data is connected to the pin sign bit out. the bit div2 controls whether it is the msb or msb/2 that is output. d3 d iv2 div2 is used in association with signpib and opbiten. this is fully explained in table xiii. when div2 = 1, the digital output is passed directly to the sign bit out pin. when div2 = 0, the digital output/2 is passed directly to the sign bit out pin. d2 reserved this bit must always be set to 0. d1 mode the function of this bit is to control what is output at the iout/ioutb pins. this bit should be set to 0 if the control bit opbiten = 1. when mode = 1, the sin rom is bypassed, resulting in a triangle output from the dac. when mode = 0, the sin rom is used to convert the phase information into amplitude information, which re- sults in a sinusoidal signal at the output (see table xiv). d0 reserved this bit must always be set to 0. the frequency and phase registers the ad9834 contains two frequency registers and two phase registers. these are described in table iii. table iii. frequency/phase registers register size description freq0 28 bits frequency register 0. when fsel bit or fselect pin = 0, this register defines the output frequency as a fraction of the mclk frequency. freq1 28 bits frequency register 1. when fsel bit or fselect pin = 1, this register defines the output frequency as a fraction of the mclk frequency. phase0 12 bits phase offset register 0. when psel bit or pselect pin = 0, the contents of this register are added to the output of the phase accumu lator. phase1 12 bits phase offset register 1. when psel bit or pselect pin = 1, the contents of this register are added to the output of the phase accumu lator. the analog output from the ad9834 is: f mclk /2 28 freqreg where freqreg is the value loaded into the selected fre quency register. this signal will be phase shifted by 2 /4096 phasereg where phasereg is the value contained in the selected phase register. consideration must be given to the relationship of the selected output frequency and the reference clock fre- quency to avoid unwanted output anomalies. access to the frequency and phase registers is controlled by both t he fselect/pselect pins and the fsel/psel control bits. if the control bit pin/sw = 1, the pins control the function; whereas, if pin/sw = 0, the bits control the function. this is outlined in tables iv and v. if the fsel/psel bits are being used, the pins should preferably be held at cmos logic high or low. control of the frequency/phase registers can be interchanged from the pins to the bits.
rev. 0 e12e ad9834 table iv. selecting a frequency register fselect fsel pin/sw selected register 0x 1 freq0 reg 1x 1 freq1 reg x0 0 freq0 reg x1 0 freq1 reg table v. selecting a phase register pselect psel pin/sw selected register 0x 1 phase0 reg 1x 1 phase1 reg x0 0 phase0 reg x1 0 phase1 reg the fselect and pselect pins are sampled on the internal falling edge of mclk. it is recommended that the data on these pins does not change within a time window of the falling edge of mclk (see figure 3 for timing). if fselect/pselect changes value when a falling edge occurs, there is an uncertainty of one mclk cycle as to when control is transferred to the other frequency/phase register. the flow charts in figures 9 and 10 show the routine for selecting and writing to the frequency and phase registers of the ad9834. writing to a frequency register when writing to a frequency register, bits d15 and d14 give the address of the frequency register. table vi. frequency register bits d15 d14 d13 d0 01 14 freq0 reg bits 10 14 freq1 reg bits if the user wishes to alter the entire contents of a frequency register, two consecutive writes to the same address must be performed, as the frequency registers are 28 bits wide. the first write will contain the 14 lsbs, while the second write will contain the 14 msbs. for this mode of operation, the control bit b28 (d13) should be set to 1. an example of a 28-bit write is shown in table vii. table vii. writing fffc000 to freq0 reg sdata input result of input word 0010 0000 0000 0000 control word write (d15, d14 = 00), b28 (d13) = 1, hlb (d12) = x 0100 0000 0000 0000 freq0 reg write (d15, d14 = 01), 14 lsbs = 0000 0111 1111 1111 1111 freq0 reg write (d15, d14 = 01), 14 msbs = 3fff in some applications, the user does not need to alter all 28 bits of the frequency register. with coarse tuning, only the 14 msbs are altered, while with fine tuning only the 14 lsbs are altered. by setting the control bit b28 (d13) to 0, the 28-bit fre quency register operates as two 14-bit registers, one containing the 14 msbs and the other containing the 14 lsbs. this means that the 14 msbs of the frequency word can be altered inde- pendent of the 14 lsbs, and vice versa. bit hlb (d12) in the control register identifies which 14 bits are being altered. exam ples of this are shown in tables viii and ix. table viii. writing 3fff to the 14 lsbs of freq1 reg sdata input result of input word 0000 0000 0000 0000 control word write (d15, d14 = 00), b28 (d13) = 0, hlb (d12) = 0, i.e., lsbs 1011 1111 1111 1111 freq1 reg write (d15, d14 = 10), 14 lsbs = 3fff table ix. writing 00ff to the 14 msbs of freq0 reg sdata input result of input word 0001 0000 0000 0000 control word write (d15, d14 = 00), b28 (d13) = 0, hlb (d12) = 1, i.e., msbs 0100 0000 1111 1111 freq0 reg write (d15, d14 = 01), 14 msbs = 00ff writing to a phase register when writing to a phase register, bits d15 and d14 are set to 11. bit d13 identifies which phase register is being loaded. table x. phase register bits d15 d14 d13 d12 d11 d0 110 x msb 12 phase0 bits lsb 111 x msb 12 phase1 bits lsb the reset function the reset function resets appropriate internal registers to 0 to provide an analog output of midscale. reset does not reset the phase, frequency, or control registers. when the ad9834 is powered up, the part should be reset. to reset the ad9834, set the reset pin/bit to 1. to take the part out of reset, set the pin/bit to 0. a signal will appear at the dac output seven mclk cycles after reset is set to 0. the reset function is controlled by both the reset pin and the reset control bit. if the control bit pin/sw = 0, the reset bit co n tro ls t he f unc ti on, whe rea s if pi n/ sw = 1, t he pi n co n trols the function. table xi. applying reset reset pin reset bit pin/sw result 0x 1n o reset applied 1x 1 internal registers reset x0 0n o reset applied x1 0 internal registers reset the effect of asserting the reset pin is seen immediately at the output, i.e., the zero to one transition of this pin is not sampled. however, the negative transition of reset is sampled on the internal falling edge of mclk.
rev. 0 ad9834 e13e the sleep function sections of the ad9834 that are not in use can be powered down to minimize power consumption. this is done using the sleep function. the parts of the chip that can be powered down are the internal clock and the dac. the dac can be powered down through hardware or software. the pin/bits required for the sleep function are outlined in table xii. table xii. applying the sleep function sleep sleep1 sleep12 pin/sw pin bit bit bit result 0x x1 no power-down 1x x1 dac powered down x0 00 no power-down x0 10 dac powered down x1 00 internal clock disabled x1 10 both the dac powered down and the internal clock disabled dac powered down this is useful when the ad9834 is used to output the msb of the dac data only. in this case, the dac is not required so it can be powered down to reduce power consumption. internal clock disabled when the internal clock of the ad9834 is disabled, the dac output will remain at its present value as the nco is no longer accumulating. new frequency, phase, and control words can be written to the part when the sleep1 control bit is active. the synchronizing clock is still active which means that the selected frequency and phase registers can also be changed either at the pins or by using the control bits. setting the sleep1 bit to 0 enables the mclk. any changes made to the registers while sleep1 was active will be seen at the output after a certain latency. the effect of asserting the sleep pin is seen immediately at the output, i.e., the zero to one transition of this pin is not sampled. however, the negative transition of sleep is sampled on the internal falling edge of mclk. the sign bit out pin the ad9834 offers a variety of outputs from the chip. the digital outputs are available from the sign bit out pin. the available outputs are the comparator output or the msb of the dac data. the bits controlling the sign bit out pin are outlined in table xiii. this pin must be enabled before use. the enabling/disabling of this pin is controlled by the bit opbiten (d5) in the control register. when opbiten = 1, this pin is enabled. note that the mode bit (d1) in the control register should be set to 0 if opbiten = 1. comparator output the ad9834 has an on-board comparator. to connect this comparator to the sign bit out pin, the signpib (d4) control bit must be set to 1. after filtering the sinusoidal output from the dac, the waveform can be applied to the co mparator to generate a square waveform. msb from the nco the msb from the nco can be output from the ad9834. by setting the signpib (d4) control bit to 0, the msb of the dac data is available at the sign bit out pin. this is useful as a coarse clock source. this square wave can also be divided by two before being output. the bit div2 (d3) in the control register controls the frequency of this output from the sign bit out pin. table xiii. various outputs from sign bit out opbiten mode signpib div2 sign bit out bit bit bit bit pin 0x xx high impedance 10 00 dac data msb/2 10 01 dac data msb 10 10 reserved 10 11 comparator output 11 xx reserved the iout/ioutb pins the analog outputs from the ad9834 are available from the iout/ioutb pins. the available outputs are a sinusoidal out- put or a triangle output. sinusoidal output the sin rom is used to convert the phase information from the frequency and phase registers into amplitude information, w hich results in a sinusoidal signal at the output. to have a sinusoidal output from the iout/ioutb pins, set the bit mode (d1) = 0. triangle output the sin rom can be bypassed so that the truncated digital out put from the nco is sent to the dac. in this case, the ou tput is no longer sinusoidal. the dac will produce 10-bit linear triangular function. to have a triangle output from the iout/ ioutb pins, set the bit mode (d1) = 1. note that the sleep pin/sleep12 bit must be 0 (i.e., the dac is enabled) when using these pins. table xiv. various outputs from iout/ioutb opbiten bit mode bit iout/ioutb pins 00 sinusoid 01 triangle 10 sinusoid 11 reserved v out max v out min 2 4 6 figure 7. triangle output
rev. 0 e14e ad9834 applications because of the various output options available from the part, the ad9834 can be configured to suit a wide variety of applications. one of the areas where the ad9834 is suitable is in modulation applications. the part can be used to perform simple modula tion such as fsk. more complex modulation schemes such as gmsk and qpsk can also be implemented using the ad9834. in an fsk application, the two frequency registers of the ad 9834 are loaded with different values. one frequency will represent the space frequency, while the other will represent the mark fre- quency. the digital data stream is fed to the fselect pin, which will cause the ad9834 to modulate the carrier fre- quency between the two values. the ad9834 has two phase registers; this enables the part to perform psk. with phase shift keying, the carrier frequency is phase shifted, the phase being altered by an amount that is related to the bit stream being input to the modulator. the ad9834 is also suitable for signal generator applications. with the on-board comparator, the device can be used to generate a square wave. with its low current consumption, the part is suitable for appli- cations in which it can be used as a local oscillator. data write see figure 10 select data sources see figure 11 v out = v refout 18 r load /r set ( 1+ (sin(2 (freqreg f mclk t/2 28 + phasereg/2 12 )))) dac output change phase? change frequency? change dac output from sin to ramp? change output at sign bit out pin? change psel/ pselect? change phase register? change fsel/ fselect? change frequency register? control register write initialization see figure 9 below no no no no yes no yes yes no yes yes yes yes yes wait 8/9 mclk cycles see timing diagram figure 2 figure 8. flow chart for initialization and operation
rev. 0 ad9834 e15e initialization apply reset write to frequency and phase registers freq0 reg = f out0 / f mclk 2 28 freq1 reg = f out1 / f mclk 2 28 phase0 and phase1 reg = (phaseshift 2 12 ) / 2 (see figure 10) set reset = 0 select frequency registers select phase registers (control register write) reset bit = 0 fsel = selected frequency register psel = selected phase register pin/sw = 0 (apply signals at pins) reset pin = 0 fselect = selected frequency register pselect = selected phase register (control register write) reset = 1 pin/sw = 0 (control register write) pin/sw = 1 using control bit using pin set reset pin = 1 using control bit using pin figure 9. initialization no write 14 msbs or lsbs to a frequency register? (control register write) b28 (d13) = 0 hlb (d12) = 0/1 write a 16-bit word (see tables viii and ix for examples) write 14msbs or lsbs to a frequency register? write to phase register? (16-bit write) d15, d14 = 11 d13 = 0/1 (choose the phase register) d12 = x d11 ... d0 = phase data write to another phase register? yes write another full 28-bit to a frequency register? write two consecutive 16-bit words (see table vii for example) (control register write) b28 (d13) = 1 write a full 28-bit word to a frequency register? data write no yes yes no yes no no yes yes figure 10. data writes
rev. 0 e16e ad9834 select data sources fselect and pselect pins being used? (control register write) pin/sw = 0 set fsel bit set psel bit set fselect and pselect (control register write) pin/sw = 1 yes no figure 11. selecting data sources grounding and layout the printed circuit board that houses the ad9834 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be separated easily. a minimum etch technique is generally best for ground planes since it gives the best shielding. digital and analog ground planes should only be joined in one place. if the ad9834 is the only device requiring an agnd to dgnd connection, then the ground planes should be connected at the agnd and dgnd pins of the ad9834. if the ad9834 is in a system where multiple devices require agnd to dgnd connections, the connection should be made at one point only, a star ground point that should be established as close as possible to the ad9834. avoid running digital lines under the device as these will couple noise onto the die. the analog ground plane should be allowed to run under the ad9834 to avoid noise coupling. the power supply lines to the ad9834 should use as large a track as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this will reduce the effects of feedthrough through the board. a microstrip technique is by far the best but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes, while signals are placed on the other side. good decoupling is important. the analog and digital supplies to the ad9834 are independent and separately pinned out to minimize coupling between analog and digital sections of the device. all analog and digital supplies should be decoupled to agnd and dgnd, respectively, with 0.1 m f ceramic capaci- tors in parallel with 10 m f tantalum capacitors. to achieve the best from the decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the de vice. in systems where a common supply is used to drive both the avdd and dvdd of the ad9834, it is recommended that the system?s avdd supply be used. this supply should have the recommended analog supply decoupling between the avdd pins of the ad9834 and agnd, and the recommended digital supply decoupling capacitors between the dvdd pins and dgnd. proper operation of the comparator requires good layout strategy. the strategy must minimize the parasitic capacitance between v in and the sign bit out pin by adding isolation using a ground plane. for example, in a multilayered board, the v in signal could be connected to the top layer and the sign bit out connected to the bottom layer, so that isolation is provided by the power and ground planes between. interfacing to microprocessors the ad9834 has a standard serial interface that allows the p art to interface directly with several microprocessors. the device uses an external serial clock to write the data/control informa- tion into the device. the serial clock can have a frequency of 40 mhz maximum. the serial clock can be continuous, or it can idle high or low between write operations. when data/ control information is being written to the ad9834, fsync is taken low and is held low while the 16 bits of data are being written into the ad9834. the fsync signal frames the 16 bits of information being loaded into the ad9834. ad9834 to adsp-21xx interface figure 12 shows the serial interface between the ad9834 and the adsp-21xx. the adsp-21xx should be set up to operate in the sport transmit alternate framing mode (tfsw = 1). the adsp-21xx is programmed through the sport control register and should be configured as follows:
rev. 0 ad9834 ?7 transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. in order to load data into the ad9834, pc7 is held low after the first 8 bits are transferred and a second serial write opera- tion is performed to the ad9834. only after the second 8 bits have been transferred should fsync be taken high again. * additional pins omitted for clarity ad9834 * fsync sdata sclk 68hc11/68l11 * pc7 mosi sck figure 13. 68hc11/68l11 to ad9834 interface ad9834 to 80c51/80l51 interface figure 14 shows the serial interface between the ad9834 and the 80c51/80l51 microcontroller. the microcontroller is oper- ated in mode ??so that txd of the 80c51/80l51 drives sclk of the ad9834, while rxd drives the serial data line sdata. the fsync signal is again derived from a bit programmable pin on the port (p3.3 being used in the diagram). when data is to be transmitted to the ad9834, p3.3 is taken low. the 80c 51/80l51 transmits data in 8-bit bytes, thus only eight falling sclk edges occur in each cycle. to load the remaining 8 bits to the ad9834, p3.3 is held low after the first 8 bits have been transmitted, and a second write operation is initiated to transmit the second byte of data. p3.3 is taken high following the completion of the second write operation. sclk should idle high between the two write operations. the 80c51/80l51 outputs the serial data in a format that has the lsb first. the ad9834 accepts the msb first (the 4 msbs being the control information, the next 4 bits being the address while the 8 lsbs contain the data when writing to a destination register). therefore, the transmit routine of the 80c51/80l51 must take this into account and rearrange the bits so that the msb is output first. * additional pins omitted for clarity ad9834 * fsync sdata sclk 80c51/80l51 * p3.3 rxd txd figure 14. 80c51/80l51 to ad9834 interface ad9834 to dsp56002 interface figure 15 shows the interface between the ad9834 and the dsp56002. the dsp56002 is configured for normal mode asynchronous operation with a gated internal clock (syn = 0, gck = 1, sckd = 1). the frame sync pin is generated inter nally (sc2 = 1), the transfers are 16 bits wide (wl1 = 1, wl0 = 0), and the frame sync signal will frame the 16 bits (fsl = 0). the frame sync signal is available on pin sc2, but needs to be inverted before being applied to the ad9834. the interface to the dsp56000/dsp56001 is similar to that of the ds p56002. * additional pins omitted for clarity ad9834 * fsync sdata sclk dsp56002 * sc2 std sck figure 15. dsp56002 to ad9834 interface ad9834 evaluation board the ad9834 evaluation board allows designers to evaluate the high performance ad9834 dds modulator with a mini mum of effort. to prove that this device will meet the user? waveform synthe- sis requirements, the user only requires a power supply, an ibm compatible pc, and a spectrum analyzer along with the evaluation board. the dds evaluation kit includes a populated, tested ad9834 printed circuit board. the evaluation board interfaces to the parallel port of an ibm compatible pc. software is available with the evaluation board that allows the user to easily pro gram t he ad9834. a schematic of the evaluation board is shown in figure 15. the software will run on any ibm compatible pc that has microsoft win95, win98, windows me, or windows 2000 nt installed. using the ad9834 evaluation board the ad9834 evaluation kit is a test system designed to simplify the evaluation of the ad9834. an application note is also avail able with the evaluation board and gives full information on oper ating the evaluation board. prototyping area an area is available on the evaluation board for the user to add additional circuits to the evaluation test set. users may want to build custom analog filters for the output or add buffers and operational amplifiers to be used in the final application. xo vs. external clock the ad9834 can operate with master clocks up to 50 mhz. a 50 mhz oscillator is included on the evaluation board. how ever, this oscillator can be removed and, if required, an external cmos clock connected to the part. power supply power to the ad9834 evaluation board must be provided exter- nally through pin connections. the power leads should be tw isted to reduce ground loops.
rev. 0 e18e ad9834 dvdd sw r3 50 dgnd dvdd out dvdd c5 0.1 f lk3 u3 8 8 7 14 c8 10 f c7 0.1 f c9 0.1 f c10 10 f j2 j3 dvdd avdd dgnd 7 agnd 18 mclk 16 iout sbout mclk 18 2 14 sclk 16 4 13 sdata 14 6 15 fsync u2 1 dvdd c6 0.1 f avdd c3 10nf dvdd c13 0.01 f c14 0.01 f lk4 5 dvdd cap 6 3 comp u1 ad9834 12 8 11 reset 4 avdd c1 0.1 f c2 0.1 f avdd 2 refout c4 0.1 f 12 sleep lk5 1 fs adjust r4 6.8k c15 20 ioutb r6 200 c12 ioutb 19 iout r5 200 c11 iout r7 300 c16 17 vin j1 sclk sdata fsync reset 10 pselect 9 fselect lk1 lk2 pselect fselect r1 10k r2 10k 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 sclk fsync sdata reset figure 16. evaluation board layout integrated circuits u3 osc xtal 50 mhz u1 ad9834bru u2 74hct244 capacitors c1, c2, c5, c6, c7, c9, c14 100 nf ceramic capacitor c3, c4, c13 10 nf ceramic capacitor c8, c10 10 m f tantalum capacitor c11, c12, c15, c16 option for extra decoupling capacitors resistors r1, r2 10 k w resistor r3 50 w resistor r4 6.8 k w resistor r5, r6 200 w resistor r7 300 w resistor links lk1, lk2, lk5 3-pin sil header lk3, lk4 2-pin sil header switch sw end stackable switch (sdc double throw) sockets psel1, fsel1, clk1 subminiature bnc iout, ioutb, sbout connector connectors j1 36-pin edge connector j2, j3 pcb mounting terminal block
rev. 0 ad9834 e19e outline dimensions 20-lead thin shrink small outline package [tssop] (ru-20) dimensions shown in millimeters 20 1 11 10 6.40 bsc 4.50 4.40 4.30 pin 1 6.60 6.50 6.40 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 compliant to jedec standards mo-153ac coplanarity 0.10
c02705e0e2/03(0) printed in u.s.a. e20e

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